PLL output
Originally uploaded by Derian le Breton.
Phased-lock loops are so hot.

Actually this has sucked quite a great deal. The simulation to generate this plot (a mere 30 microseconds of data!) took about four hours to run. Before this, I was very unsure that the entire loop would work properly. The individual blocks can be tested in about 15 minutes each, but my charge-pump and loop filter were acting strangely in the initial tests...

In any case, it works! Yay!
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